In many data processing systems it may be desirable to phase align two signals, or to have a predetermined phase difference between them. For example, in DDR PHY (double date rate physical layer) there is a requirement to shift the clock input by both 360° and by 90° for effective data capture.
In these systems the phase difference is provided by delaying a clock signal by a predetermined amount using a delay locked loop DLL. The delay in the DLL is provided by multiple basic delay stages arranged in a chain, the delay across the whole chain being set to one clock cycle. The delay chain may be designed from CMOS or CML (current-mode logic) styles of inverters, CML stages generally being preferred over CMOS as they show better power supply noise immunity. As the delay of these CML stages vary with PVT (process, Voltage and temperature) calibration is needed to keep the delay constant or nearly constant across these different PVTs. Adjustment devices such as binary weighted capacitive or resistive load inside the CML stages may be used to adjust the delay.
In devices of the prior art the phase difference between the clock signal passing through the chain and the clock signal passing through a bypass line has been compared during calibration using an analogue comparator. An analogue comparator according to the prior art it shown in FIG. 1a along with a timing diagram FIG. 1b showing the signals.
In the analogue comparator of FIG. 1a there are two inputs that receive signals one output1, that being the output of the delay chain and the other, output2 being an output from the bypass path. These signals are passed into an exclusive OR gate 12 which generates a signal Y indicative of whether these values are the same or are different and a signal YB which is the inverted value of Y.
These signals Y, YB are then input to averaging circuit 14 which forms an average of these values. A comparison is then done using comparator 16. The averaging circuit 14 is present to prevent or at least impede false results due to jitter. An analogue comparator is an accurate way of comparing the signals but it takes time to perform each comparison due to the averaging and the desire to allow the signals to settle.
Looking at FIG. 1b we see that where the signals are nearly aligned the output Y is positive for very little of the time whereas the output YB is positive for a lot of the time. Thus, the average of YB is far greater than the average value of Y. As the signals get out of phase this difference reduces until at a 90° phase difference the signals cross over and the average value of Y starts to become greater than the average value of YB. This analogue comparator therefore provides a very good way of detecting a quarter phase change, that is a phase change of either 90° or 270°. It cannot be used to detect any other phase change.
Thus, in a device of the prior art where a 360° phase change is required an output signal will be taken from a quarter of the length of the delay chain and the analogue comparator is used to determine when the signal is 90° out of phase. It is then assumed that the whole delay chain has a delay of 4 times this, that is 360°. This is acceptable provided the delay stages are well matched.
In order for the analogue comparator 10 to be able to produce an accurate result a time of about of 500 nanoseconds per reading is required. This is a significant time and makes the calibration a lengthy process. For this reason, in devices of the prior art the adjustments to the delay stages are initially made in large steps and a rough estimate found, whereupon the calibration is performed again around this point in smaller steps.
It would be desirable to be able to make an accurate calibration in less time.